Circuit with multiple output voltages for multiple analog to digital converters

ABSTRACT

A circuit for generating at least two output voltages in response to an input current. A first stage comprises a first impedance for providing a first output voltage when the input current passes through the first impedance. At least a second stage comprises a second impedance coupled to the first impedance, wherein the second impedance provides a second stage voltage when the input current passes through the second impedance. At least a second output voltage is equal to the sum of the second stage voltage and the first output voltage. The second stage further comprises a second stage shunt operable to shunt the input current away from the second impedance when the magnitude of the second output voltage is above a predetermined amount.

This application is a divisional application of Ser. No. 08/775,958, filed Jan. 3, 1997, now U.S. Pat. No. 5,952,855.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to circuits for use with analog-to-digital converters (ADCs) and, in particular, to circuits that provide multirange output voltages for multiple ADCs.

2. Description of the Related Art

ADCs are used to convert an analog voltage to a digital signal. In some applications, the analog voltage has a magnitude which is proportional to the magnitude of an input signal to be monitored. For example, the input signal may be an input current flowing in a given current path. This input current may drive a primary winding of a current transformer, which produces a current in the secondary winding of the transformer, which is proportional to the input current. The secondary winding current may be applied to a known impedance, such as a resistance, to provide an analog voltage, which has a magnitude proportional to the magnitude of the secondary winding current and, thus, to the magnitude of the input current. The windings of the transformer and value of the resistance may be selected so that the range of the analog voltage for the expected range of the input current will be within the analog voltage input range of an ADC, which in turn converts the analog voltage to a digital signal, which can then be used to monitor the magnitude of the input current.

One problem with such conventional circuits utilizing ADCs is that the input signal to be monitored may have wide magnitude variations, which requires an ADC having a large dynamic range in order to accurately measure the signal's magnitude at both low and high levels. Unfortunately, ADCs capable of measuring a large dynamic range, for example larger than 10 bits, can be relatively expensive and thus unattractive.

Another problem exists in some configurations in which the secondary winding current is forced through a relatively large resistance, which causes a relatively large voltage signal to be produced when the secondary winding current is passed through the resistance. This imposes a large burden on the transformer, which could result in saturation, causing distortion and thus reducing the efficiency and performance of the transformer. Such large voltage signals can also cause damage to the ADC.

SUMMARY OF THE INVENTION

A circuit for generating at least two output voltages in response to an input current. A first stage comprises a first impedance for providing a first output voltage when the input current passes through the first impedance. At least a second stage comprises a second impedance coupled to the first impedance, wherein the second impedance provides a second stage voltage when the input current passes through the second impedance. At least a second output voltage is equal to the sum of the second stage voltage and the first output voltage. The second stage further comprises a second stave shunt operable to shunt the input current away from the second impedance when the magnitude of the second output voltage is above a predetermined amount.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a circuit in accordance with the present invention; and

FIG. 2 depicts the output voltages of the circuit of FIG. 1 versus an input current.

DESCRIPTION OF THE PREFFRRED EMBODIMENT

Referring now to FIG. 1, there is shown a schematic diagram of a circuit 100 in accordance with the present invention. Circuit 100 includes a current transformer 102 having primary winding or coil L₁ and secondary winding or coil L₂, which have a certain turn ratio to one another. Transformer 102 further includes core 105. Each terminal of secondary winding L₂ is coupled to node 110 through a respective diode of bridge rectifier 150.

Circuit 100 further comprises stages 121, 122, and 123. Stage 121 comprises resistor R₁, coupled between nodes 110 and 111. Stage 122 comprises resistor R₂, coupled at one terminal to node 112, and at its other terminal to node 111, to a terminal of resistor R₁, to a terminal of resistor R₆, and to the emitter of transistor Q₁. Resistor R₆ is coupled at its other terminal to the base of transistor Q₁, to a terminal of resistor R₈, and to the emitter of transistor Q₃. Resistor R₈ is coupled at its other terminal to the base of transistor Q₃ and to the anode of zener diode Z₁. The collector of transistor Q₃ is coupled to a terminal of resistor R₁₀. The other terminal of R₁₀ is coupled to the cathode of zener diode Z, and to a terminal of resistor R₄. Resistor R₄ is coupled to the collector of Q₁, to node 112, and to resistor R₂ through resistor R₇.

Stage 123 comprises resistor R₃, coupled at one terminal to node 113, and at its other terminal to node 112, to a terminal of resistor R₂, to a terminal of resistor R₇, and to the emitter of transistor Q₂. Resistor R₇ is coupled at its other terminal to the base of transistor Q₂, and to a terminal of resistor R₄. Resistors R₄ and R₇ are thus components of both stages 122 and 123. Resistor R₄ is coupled at its other terminal to the cathode of zener diode Z₁, to resistor R₁₀, to resistor R₉, and to the emitter of transistor Q₄. Resistor R₉ is coupled at its other terminal to the base of transistor Q₄ and to the anode of zener diode Z₂. The collector of transistor Q₄ is coupled to a terminal of resistor R₁₁. The other terminal of resistor R₁₁ and the cathode of zener diode Z₂ are coupled to resistor R₅ and to each terminal of secondary winding L₂ through a is respective diode of bridge rectifier 150. The other terminal of resistor R₅ is coupled to the collector of transistor Q₂, to resistor R₃, and to node 113.

In one embodiment, the resistors of circuit 100 have the following values: R₁ =12.5 Ω; R₂ =187.5 Ω; R₃ =3 KΩ; R₁ =866 Ω; R₅ =13.7 KΩ; R₆ =10 KΩ; R₇ =10 KΩ; R₈ =10KΩ; R₉ =10KΩ; R₁₀ =82 Ω; R₁₁ =82 Ω. Zener diodes Z, and Z₂ each have reverse breakdown voltages of 15 V.

First current I₁, driven by current source 101, flows through primary winding L₁ of transformer 102. A proportional alternating current 13 is thereby generated at secondary winding L₂. Alternating current 13 is rectified by bridge rectifier 150 to generate rectified second current I₂, which is applied to stage 123 at the junction of resistors R₁₁, R₅, and zener diode Z₂. Secondary winding L₂ combined with bridge rectifier 150 is thus a current source that generates second current I₂. Circuit 100 outputs three voltages, V₁, V₂, and V₃, at nodes 111, 112, and 113, respectively, each of which is measured with respect to ground or common node 110. Voltages V₁, V₂, and V₃ are analog voltage signals that are applied to ADCs 1, 2, and 3, respectively. Each ADC, in one embodiment, is a 10-bit ADC. Thus, the magnitude of each of voltages V₁, V₂, and V₃ is converted to a 10-bit digital number by its respective ADC at each sampling interval. Each of voltages V1, V₂, and V₃ thus has a dynamic range of 10 bits. Circuit 100 is configured to provide an 18-bit dynamic range for the measurement of current I₂ (and thus of current I₁). As will be appreciated, since circuit 100 may be utilized to monitor the magnitude of second current I₂ and thus of first current I₁, either of currents I₁ or I₂ may be considered as the input current converted to corresponding voltages V₁, V₂, and V₃ and thus monitored by ADCs 1, 2, and 3. For purposes of the present description, rectified current I₂ is considered to be the input current, generated by the current source consisting of secondary winding L₂ and rectifier 150, the magnitude of which is to be monitored by ADCs 1, 2, and 3.

To provide an 18-bit dynamic range utilizing three 10-bit ADCs, the magnitudes of voltages V₁, V₂, and V₃ are selected such that V₃ is 4 bits, or 16 times (2⁴ =16), larger than V₂, and V₂ is 16 times larger than V₁. For lower magnitudes of current I₂, current 12 flows through each of resistors R₃, R₂, and R₁. The values of these resistors are selected so that voltages V₁, V₂, and V₃, at nodes 111, 112, and 113, are progressively larger by factors of 16. Thus, to ensure that V₂ =16 A V₁, the values of the resistors are selected such that R₂ +R₁ =16 A R₁. Similarly, to ensure that V₃ =16 A V₂, the values of the resistors are selected such that R₃ +R₂ +R₁ =16 A (R₂ +R₁). Thus. stages 121, 122, 123 each provide a resistance for current I₂ to be multiplied by to provide the appropriate output voltage for that stage. For example, stage 123 provides resistor R₃. When current 12 flows through resistor R₃, then the incremental voltage produced thereacross, when added to voltage V₂ with which it is in series, provides voltage V₃, having a magnitude 16 times larger than that of V₂.

Referring now to FIG. 2, there is depicted the output voltages V₁, V₂, and V₃ of circuit 100 of FIG. 1 versus current I₂. In one embodiment, each of ADCs 1, 2, and 3 is configured to operate within a range of 50 mV to 1.25 V, the maximum reading of each ADC. At low currents of approximately 100 μA, V₁ ≈1.25 mV, V₂ ≈20 mV, and V₃ ≈320 mV. Thus, at this current magnitude, the most sensitive reading can be provided by ADC 3 measuring V₃. At a higher current I₂ magnitude, such as 1 mA, V₃ is larger than 1.25 V and is thus too large for ADC 3 to provide an accurate measurement. Thus, at this higher current, the reading of the magnitude of V₂ provided by ADC 2 may be utilized. At higher currents, such as 10 mA, ADC 1, which measures V₁, may be utilized.

ADCs 1, 2, and 3 may be utilized in this fashion to provide an effective 18-bit resolution measurement of the magnitude of currents I₂ and I₁. When input current magnitude is lower, greater resolution may be provided by using the lower 10-bits of the 18-bit resolution provided by ADC 3. When input current magnitude is highest, the upper 10-bits of the 18-bit overall resolution may be obtained from ADC 1. As will be appreciated by those skilled in the art. ADCs 1, 2, and 3 may be utilized in this fashion by always selecting the reading from the ADC having the largest-magnitude input voltage that is also not greater than the maximum allowable input voltage for ADCs. For example, a program running on a processor may constantly monitor the reading of V₁ provided by ADC 1. Whenever V₁ is greater than approximately 78 mV (the point at which V₂ =1.25 V), ADC 1 will be utilized to measure the input current. Whenever V₁ is greater than approximately 5 mV (the point at which V₃ =1.25 V) but less than approximately 78 mV, ADC 2 will be utilized to measure the input current. Whenever V₁ is less than approximately 5 mV, ADC 3 is utilized to measure the input current.

If stages 122 and 123 consisted exclusively of resistors R₂ and R₃, then, at higher input currents, for example when ADC 1 is utilized to measure V₁, voltages V₂ and V₃ would be 16 and 256 times larger, respectively, than V₁. Such large voltages could damage ADCs 2 and 3, and also place an undesirable burden on transformer 102, as explained previously. Therefore, in the present invention. stages 122 and 123 provide shunting means 132 and 133 which shunt most of current I₂ away from the stages respective resistors R₂ and R₃. In stage 122, shunting means 132 consists of the components of stage 122 other than resistor R₂. In stage 123, shunting means 133 consists of the components of stage 123 other than resistor R₃. As illustrated in FIG. 2, at an input current I₂ of approximately 1 mA, voltage V₃ is approximately 3 V, and, as input current I₂ increases, voltage V₃ starts to "fold back" to a voltage having a slightly larger magnitude than that of V₂ by the time input current I₂ is approximately 1.3 mA, since most of current I₂ is shunted by shunting means 133 so that it no longer passes through R₃. Similarly, at an input current I₂ of approximately 15 mA, voltage V₂ is approximately 3 V, and, as input current I₂ increases, voltage V₂ starts to fold back to a voltage having a slightly larger magnitude than that of V₁ by the time input current I₂ is approximately 20 mA, since most of current I₂ is shunted by shunting means 132 so that it no longer passes through R₂.

Shunting means 133 and 132 operate as follows, as will be appreciated by those skilled in the art. At current 12 magnitudes below 1 mA, both shunting means are "off," and thus allow I₂ to pass through resistors R₃ and R₂. When shunting means 133 and 132 are off, their constituent zener diodes and transistors are off, and the shunting means appear as open circuits to current I₂. As current I₂ reaches and begins to exceed 1 mA, the voltage drop across resistor R₅ becomes high enough such that the voltage at the terminal of resistor R₅ coupled to the cathode of zener diode Z₂ turns on Z₂, causing current I_(z2) to flow therethrough. Current I_(z2) flows through resistor R₉, causing a voltage drop thereacross which turns on transistor Q₄. Current thus flows through transistor Q₄ and thence through R₄ and R₇. The voltage drop across R₇ is sufficient to turn on transistor Q₂, which thus shunts away from R₃ most of current I₂, causing the voltage V₃ to "fold back" as illustrated in FIG. 2. At this point. V₃ is slightly larger than V₂.

Most of current I₂ thus flows through Q₂ instead of through R₃ for current magnitudes above approximately 1.3 mA. At this point none of the current from Q₄ flows down into shunting means 132, since Q₃ and Z₁ of shunting means 132 are off because the voltage across R₂ is insufficient to allow current to flow through zener diode Z₁. Transistor Q₁ thus remains turned off, and current I₂ flows through stage 123 and thence through resistors R₂ and R₁, to develop voltages V₂ and V₁, as before. As current I₂, reaches and begins to exceed 15 mA, the voltage drop across resistor R₄ becomes high enough such that the voltage at the terminal of resistor R₄ coupled to the cathode of zener diode Z₁ turns on Z₁, causing current I_(Z1), to flow therethrough. Current I_(Z1), flows through resistor R₈, causing a voltage drop thereacross which turns on transistor Q₃. Current thus flows through transistor Q₃ and thence through R₆. The voltage drop across R₆ is sufficient to turn on transistor Q₃, which thus shunts away from R₂ most of current I₂, causing the voltage V₂ to "fold back" as illustrated in FIG. 2. At this point. V₂ is slightly larger than V₁.

Resistors R₄ and R₅ along with zener diodes Z₁ and Z₂, are the principal components of circuit 100 that set the fold back points, or maximum voltages, for ADCs 2 and 3, respectively. Resistors R₁₀ and R₁₁ are used to reduce the power loss in transistors Q₃ and Q₄ at higher current levels.

Thus, circuit 100 is a circuit for generating output voltages V₁, V₂, and V₃ in response to an input current I₂. In one embodiment, circuit 100 comprises a first stage 121 comprising a first impedance R₁ for providing a first output voltage V₁ when the input current 12 passes through the first impedance R₁, and a second stage 122. Second stage 122 comprises a second impedance R₂ and a second stage shunt means 132, wherein the second impedance R₂ provides a second stage voltage V_(R2) =(V₂ --V₁) when the input current I₂ passes through the second impedance R₂ and the second stage shunt means 132 is for shunting the input current I₂ away from the second impedance R₂ when the input current I₂ is above a predetermined amount (in the example given above, 15 mA). The second impedance R₂ is coupled to the first impedance R₁ so that the second stage voltage V_(R2), when added to the first output voltage V₁, provides a second output voltage V₂. The second stage shunt means 132 preferably comprises a transistor Q₁ for shunting the input current I₂ away from the second impedance R₂. The second output voltage V₂ is preferably a predetermined multiple (e.g., 16) of the first output voltage V₁.

In further embodiments, additional stages may be added, such as third stage 123. Third stage 123 comprises a third impedance R₃ and a third stage shunt means 133, wherein the third impedance R₃ provides a third stage voltage V_(R3) when the input current 12 passes through the third impedance R₃ and the third stage shunt means 133 is for shunting the input current away from the third impedance when the input current is above a second predetermined amount (e.g., 1mA), wherein the third impedance is coupled to the second impedance so that the third stage voltage V_(R3), when added to the second output voltage V₂, provides a third output voltage V₃.

Thus, circuit 100 of the present invention provides for reduced power requirements and a reduced burden on the transformer. Central processing units (CPUs) having multiple 10-bit ADCs are also relatively inexpensive, so that the current invention provides for a larger dynamic ADC range than is possible with a single ADC, at a lower cost.

Those skilled in the art will appreciate that alternative embodiments of the present invention may utilized a number of stages other than three. For example, a four-stage circuit may be utilized with four ADCs and four output voltages, in which three of the four stages provide a resistor and a shunting means. Additionally, in alternative embodiments, ADCs having a resolution other than 10-bits may be utilized. ADCs may also be combined with overlaps other than 4 bits, to provide an effective resolution other than 18 bits. For example, three 10-bit resolution ADCs may be utilized, with voltages V₁, V₂, and V₃ separated by a factor of 32 (5 bits) rather than 16 (4 bits), for an overall resolution of 20 bits instead of 18 bits. Alternatively, three 12-bit resolution ADCs may be utilized, with voltages V₁, V₂, and V₃ separated by a factor of 16, for an overall resolution of 20 bits instead of 18 bits.

It will be understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated above in order to explain the nature of this invention may be made by those skilled in the art without departing from the principle and scope of the invention as recited in the following claims. 

What is claimed is:
 1. A method for generating at least two variable output voltages in response to a variable input current, comprising the steps of:providing a first output voltage when the variable input current passes through a first impedance; providing a second stage voltage when the variable input current passes through a second impedance, wherein a second output voltage equal to the sum of the first output voltage and the second stage voltage is produced; and automatically shunting the variable input current away from the second impedance while still applying the variable input current to the first impedance when the magnitude of the second output voltage is above a predetermined amount.
 2. The method of claim 1, wherein the step of shunting the input current away from the second impedance includes activating a transistor when the input current is above a predetermined amount.
 3. The method of claim 1, further comprising the step of providing a third stage voltage when the input current passes through a third impedance, wherein a third output voltage equal to the sum of the third stage voltage and the second output voltage is produced.
 4. The method of claim 3, further comprising the step of shunting the input current away from the third impedance when the magnitude of the third output voltage is above a second predetermined amount.
 5. The method of claim 4, wherein the step of shunting the input current away from the third impedance includes activating a second transistor when the input current is above a predetermined amount. 